This application claims the benefit of priority to Italian patent application number T02002A000811, filed on Sep. 18, 2002.
1. Field of the Invention
The invention relates to output buffers, and particularly to controlling an internal VDDQ reference voltage around a target value when short capacitor charge times are desired.
2. Discussion of the Related Art
In integrated devices, an internal power source may be viewed as an RLC model (resistance-inductance-capacitance) between an external pin and integrated transistors. A schematic representation of a simplified circuit according to this model is illustrated at FIG. 1. FIG. 1 shows an external voltage or VDDQGEN (or VDDQ_GEN in FIG. 1) connected through inductance L to resistors Ri, . . . , Rn and capacitors Ci, . . . , Cn, wherein the capacitors Ci, . . . , Cn power the internal voltages or VDDQinternal (or INTERNAL_VDDQ) in FIG. 1). With this model in mind, problems are observed as being caused by inductance and resistance when it is desired to charge a relatively large capacitance in a very short time, i.e., on the order of nanoseconds (ns).
In these cases, a large amount of current is flowed involving a significant drop on the resistance. If left uncontrolled, fluctuations of the power current dropped at the resistance induce drops or overshoots of the values of the internal power VDDQinternal (by the inductance).
These drops and overshoots may generate variations of the values of VDDQinternal resulting in undesirable consequences. For example, an uncontrolled drop of VDDQinternal below a trigger point voltage may turn off p-mos transistors that take VDDQ as a high reference voltage. Also, an eventual VDDQinternal drop below the trigger point voltage may slow output switching for those transistors that have Vgate equal to zero. This undesired effect may occur due to delays associated with waiting for the VDDQ to recover before detecting the Vout logic value to be xe2x80x9c1xe2x80x9d.
The charging and discharging of the output data pin, i.e., characterized by a relatively large capacitance, is one of the situations wherein this effect may produce significant undesirable effects. To prevent these effects, current control may be provided when the output buffers are switching on.
The control of the VDDQ absorbed current may be achieved by different techniques. One technique is controlling the p-mos buffer turn on. The buffer elements are not switched on in digital mode, as is typical with traditional architectures, but their VGS absolute values rise in time with a pending control.
FIG. 2, e.g., schematically illustrates a conventional architecture. The conventional architecture of FIG. 2 has VDDQinternal connected to the p-mos (P4) transistors M0 and M3. The p-mos transistor M3 is connected to n-mos (N) transistor M2. The p-mos transistor M0 is connected to n-mos (N) transistor M1. The n-mos transistors M1 and M2 are each also connected to ground. An input control signal dataout (or OUT_DATA in FIG. 2) controls each of the p-mos transistor M3 and the n-mos transistor M2. The output of the p-mos transistor M3 controls each of p-mos transistor M0 and n-mos transistor M1. The output of the p-mos transistor M0 is connected to capacitor Cout.
The discharge current may be controlled, as in the circuit of FIG. 2, by the turning to ground of the gate of the p-mos transistor M0 when dataout is low. In this way, current absorbed by the out buffer, when the output data changes from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d, has a continuous profile in the time without abrupt variations.
It is recognized in the present invention that a determination of the value of the gate discharge current may be achieved by modifying the circuit of FIG. 2 in different ways according to FIG. 3. These modifications each include insertion of a device D between the output of p-mos transistor M6 corresponding to p-mos transistor M3 of FIG. 2, and n-mos transistor M4, corresponding to n-mos transistor M2 of FIG. 2. The output of p-mos transistor M6 still controls p-mos transistor M7, corresponding to p-mos transistor M0 of FIG. 2. The n-mos transistor M5, corresponding to n-mos transistor M1 of FIG. 2, is now controlled by the digital N-control. Specific modifications include adding a discharge resistor as the device D, as in the circuit of FIG. 4, or adding a mirrored current transistor as the device D, as in the circuit of FIG. 5.
Referring to FIG. 4, the discharge resistor (RP) R1 may be inserted between the output of the p-mos transistor M10 corresponding to the p-mos transistor M3 of FIG. 2, and the n-mos transistor M8 corresponding to the n-mos transistor M2 of FIG. 2. The output of p-mos transistor M10 would still control the p-mos (P4) transistor M11 corresponding to the p-mos transistor M0 of FIG. 2. The n-mos transistor (N) M9 of the circuit of FIG. 4, and corresponding to the n-mos transistor M1 of FIG. 2, would be controlled by digital N-control, rather than by the output of p-mos transistor M10 as in the circuit of FIG. 2.
Referring to FIG. 5, the mirrored current transistor M16 may be inserted between the output of the p-mos transistor M14 corresponding to the p-mos transistor M3 of FIG. 2, and the n-mos transistor M12 corresponding to the n-mos transistor M2 of FIG. 2. The mirrored current transistor M16 is controlled by Imirror (or I_MIRROR in FIG. 5). The output of p-mos transistor M14 would still control the p-mos (P4) transistor M15 corresponding to the p-mos transistor M0 of FIG. 2. The n-mos transistor (N) M13 of the circuit of FIG. 5 would be controlled by digital N-control, rather than by the output of p-mos transistor M14 as in the circuit of FIG. 2.
The solutions described above with reference to FIGS. 4 and 5 may solve the problem of VDDQ drop, because the buffer turn on is controlled. However, these solutions are not preferred herein for avoiding overshoot of VDDQ when Cout is charged and the current goes to zero. These solutions do not involve an active control because the resistance value of R1 or mirrored current value of M16 are determined at the time the circuit is designed and are not later modifiable. It is desired to have an active control which prevents the VDDQ drop and overshoot problems described above.
In view of the above, an output buffer switch-on control is provided for avoiding internal VDDQ drop and overshoot with a limited circuital overhead. Eventual VDDQ variations are automatically corrected by active controlling implemented by an output voltage feedback arrangement.
A particularly preferred output buffer switch-on control circuit includes at least four transistors. The first transistor has a first terminal connected to an internal voltage line and is controlled by an output data source. The second transistor has a first terminal connected to the internal voltage line and is controlled by a second terminal of the first transistor. The second transistor also has a second terminal connected to a first terminal of an output capacitor. The third transistor is controlled by the output data source and has a first terminal connected to a common voltage. The fourth transistor is digitally controlled and has a first terminal connected to the second terminal of the second transistor and has a second terminal connected to the common voltage. The switch-on control circuit further includes a discharge current control circuit connected between a second terminal of the first transistor and a second terminal of the third transistor. The discharge current control circuit is advantageously preferably actively-controlled.
The discharge current control circuit preferably includes a discharge resistor and a mirrored current transistor. The mirrored current transistor is preferably controlled by a connection between the second terminal of the second transistor and the first terminal of the fourth transistor. The mirrored current transistor preferably includes a first terminal connected to the second terminal of the first transistor and preferably also includes a second terminal connected to the discharge resistor. The discharge resistor is preferably connected between the mirrored current transistor and the third transistor. The first and second transistors preferably comprise p-type MOSFETS, and the third and fourth transistors comprise n-type MOSFETS. A second terminal of the output capacitor is preferably connected to the common voltage.